1. Field of the Invention
The present invention relates to a handler for testing semiconductor devices, and more particularly, to a handler for testing semiconductor devices which connects semiconductor devices to test sockets connected to an external testing apparatus, to enable the semiconductor devices to be tested, sorts the tested semiconductor devices, based on the results of the test, and stores the sorted semiconductor devices.
2. Discussion of the Related Art
Generally, memory or non-memory semiconductor devices or modular ICs, each of which includes memory or non-memory semiconductor devices appropriately arranged on a substrate to form a circuit, are subjected to various tests after production thereof, but prior to shipment thereof. For such a test, a handler is used which automatically electrically connects semiconductor devices or modular ICs, as mentioned above, to an external testing apparatus.
Many of such handlers can not only perform a general performance test under a room temperature condition, but can also perform a high-temperature or low-temperature test after forming an extremely low or high temperature atmosphere in a sealed chamber using an electric heater or a liquefied nitrogen spray system, to determine whether or not a semiconductor device or modular IC subjected to the test can perform normal functions even under extreme temperature conditions.
Korean Patent Publication No. 10-0384622, the application of which was filed in the name of the present application, (published on May 22, 2003) discloses a handler for testing semiconductor devices, which includes a plurality of chambers configured without causing an increase in the overall size of the handler and a complexity in the structure of the handler, to enable a large amount of semiconductor devices to be efficiently tested within a short time.
The disclosed handler includes a chamber station including two chamber layers, namely, an upper chamber layer and a lower chamber layer, on each of which chambers having different functions are horizontally arranged. Each chamber layer includes a pre-heating chamber for pre-heating or pre-cooling semiconductor devices, a test chamber for performing a test for the pre-heated or pre-cooled semiconductor devices, and a defrosting chamber for returning the semiconductor devices to room temperature. In accordance with this arrangement, it is possible to test semiconductor devices of a number corresponding to two times the number of semiconductor devices simultaneously testable at one time in conventional cases.
That is, in conventional memory handlers developed prior to the above-mentioned handler of the present applicant, one test board provided with a plurality of test sockets is arranged in a single test chamber, for execution of a test. In this case, accordingly, only one test tray must be used which is connected to the test board.
On the other hand, in the handler developed by the present applicant, two test boards can be used which are mounted to respective test chambers. Accordingly, it is possible to test semiconductor devices of a number corresponding to two times the number of semiconductor devices simultaneously testable at one time in conventional cases.
Hereinafter, the test procedure carried out in the handler will be described in brief.
First, semiconductor devices loaded in user trays in a loading station are sequentially fed to an exchanging station by a picker. In the exchanging station, the fed semiconductor devices are aligned at a uniform interval by an aligner, and are then loaded in test trays made of heat-resistant metal. Thereafter, the test trays are sequentially fed to the test chamber, so that the semiconductor devices loaded in the test trays will be sequentially subjected to an electrical test. In this case, the test trays are distributed to two layers in a preheating chamber, before entering the test chamber, so that the test trays on respective layers can be connected to the test boards arranged in two layers in the test chamber, respectively, so as to be subjected to the test.
The test-completed test trays are sequentially re-fed to the exchanging station after passing through a defrosting chamber. In the exchanging station, the tested semiconductor devices of each test tray are unloaded from the test tray. The unloaded semiconductor devices are then received in associated user trays after being sorted in accordance with the results of the test.
However, the above-mentioned conventional handler has the following problems.
First, the procedure for loading/unloading semiconductor devices in/from test trays in the exchanging station is more or less complex. Also, the configuration to achieve this loading/unloading procedure is more or less complex.
That is, in the above-mentioned handler, the semiconductor device pitch in the user trays is different from the semiconductor device pitch in the test trays. For this reason, in the above-mentioned handler, the semiconductor devices carried by the user trays must be loaded in the aligner in the exchanging station so that they are aligned at a pitch corresponding to the semiconductor device pitch of the test trays. The aligner is then horizontally moved to a place where a test tray is arranged, to feed the semiconductor devices to the test tray. In order to unload semiconductor devices from a test-completed test tray, the aligner in an empty state may be moved to the test tray.
When the procedure for loading/unloading semiconductor devices in/from test trays in the exchanging station is complex, as mentioned above, the working time in the exchanging station is lengthened. As a result, the number of simultaneously testable semiconductor devices is greatly limited.
Second, typically, diverse handlers, which use different test boards with different numbers of test sockets, respectively, are manufactured by handler manufacturers to satisfy diverse demands of diverse consumers, that is, diverse semiconductor device manufacturers. However, semiconductor device manufacturers desire to use a handler, to which diverse test boards with different numbers of test sockets can be mounted (such a test board is manufactured by a tester manufacturer, and is separably mounted to a handler, for a test).
For example, although the current tendency of semiconductor device manufacturers is to require a handler which can use a plurality of test boards each provided with 128 test sockets (also, referred to as “128-para test boards”), taking into consideration the productivity in future, the semiconductor device manufacturers are also requiring a handler which can use a plurality of test boards each provided with 64 test sockets (also, referred to as “64-para test boards”). To this end, it is necessary to provide a handler compatible with both the 64-para test board and the 128-para test board.
Meanwhile, the pitch of test sockets must be varied depending on the kind of semiconductor devices to be tested. For this reason, handlers must use diverse carrier pitches because the carrier pitch of test trays is varied depending on the test socket pitch.
In conventional handlers, however, the size and structure of test trays functioning to feed semiconductor devices are standardized. Furthermore, the constituent elements of a test chamber where test boards are mounted, for example, guide rails guiding movement of test trays and a driver, cannot be varied in position. As a result, such a conventional handler is not compatible with both the 64-para test board and the 128-para test board. Thus, such a conventional handler must execute a test with a single, fixed carrier pitch.